Many traditional memory architectures usually implement a linear address space. On each clock cycle random access to any word in the address space is possible. Although such architecture is general and allows storage of matrices, the architecture is not suitable for efficient and/or robust matrix processing in digital signal processing (DSP) hardware (HW). Further, parallel access to several matrix elements is not possible limiting the maximum memory bandwidth. Random access to complete address space allows undesirable effects such as overlapping matrices and memory fragmentation.
US 2008316835 discloses an N-dimension addressable memory optimized for random matrix operations. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
According to FIGS. 4A and 4B of US 2008316835 there is illustrated an addressing scheme for a 2-Dimension Word Addressable (DWA) memory in accordance with at least one embodiment. In FIG. 4A, Address (1) (Addr (1)) is used to address sixteen 2-bit words. Each of the 2-bit words (e.g., 0-15) represents a 2-element row of a target matrix data. In FIG. 4B, Address (2) (Addr (2)) is used to address eight 4-bit words (e.g., 0-7). Each of the 4-bit words represents a 4-element column of a target matrix data. For exampled for a read operation, a 4-bit output of the column data in matrix 1, column 1 can then be obtained in a single operation. Likewise, for a write operation, 4-bit data can be stored to matrix 1, column 1 in a single operation.
If an application requires the reading of bit 2 of the words 0, 1, 2 and 3 as indicated by reference 120, in FIG. 1B of US 2008316835 using a conventional single ported memory, it will require four memory access cycles to read all four words. Then, additional operations will be needed to extract the bit 2 information individually. In contrast, an exemplary embodiment of US20083116835 allows for the data to be accessed in a single memory cycle.
Prior art document U.S. Pat. No. 6,604,166 shows an n-dimensional addressable memory arrangement which allows parallel access to of a plurality of data elements along any dimension of an n-dimensional data array. To enable parallel access of s data elements along any dimension, the data elements of n-dimensional data array are mapped to s parallel memory banks in such a way that consecutive s data elements along any dimension are mapped to different memory banks. This mapping is defined by two functions, which define the memory bank number and location within a memory bank for each data element in n-dimensional data array. Generic function pairs are described for all combinations of (n, s). Two particular instances of the mapping, namely circular permutation (rotation) along 0'th dimension and dyadic permutation along 0th dimension have been discussed in detail.
The basic architecture for proposed memory for (m,n)-hyper-matrix is shown in FIG. 3 of U.S. Pat. No. 6,604,166. For storing the s-data elements of any data vector into the memory banks, the n-dimensional starting index, the dimension along which the data is to be stored, and the s data elements are provided to this architecture. For reading s data elements in parallel, the n-dimensional starting index and the dimension of access are provided to the memory architecture. Based on these, the addresses for all of s banks 34 are computed by address generation logic 31 and issued to the banks 34 after carrying out a permutation (rearrangement) by permutation logic 32, which ensures that only the required locations are accessed in each bank. The inverse permutation logic 33 for the data read from (written into) the memory is inverse (same) of Permutation logic 32 for addresses.
The above documents are associated with certain restrictions as to how matrix calculations can be performed.